Integrated circuits are widely used for consumer, commercial and other applications. As is well known to those having skill in the art, an integrated circuit may include a large number of active devices, such as transistors, on an integrated circuit substrate. As the integration density of integrated circuit devices continues to increase, effects may be produced that can degrade the performance of the integrated circuit transistors.
One widely used integrated circuit transistor is an integrated circuit field effect transistor. As is well known to those having skill in the art, an integrated circuit field effect transistor generally includes a substrate, such as a semiconductor substrate, and an isolation region, such as a shallow trench isolation region in the substrate, which defines an active region in the substrate. Spaced apart source/drain regions are provided in the active regions, and a channel region is provided in the active region between the spaced apart source/drain regions. An insulated gate is provided on the channel region. The insulated gate generally includes a gate insulating layer and a gate electrode. Source/drain and gate contacts also may be provided for the source/drain and gate regions, respectively. The source/drain and gate contacts may include silicide. The design and fabrication of integrated circuit field effect transistors is well known to those having skill in the art, and need not be described further herein.
As the integration density of integrated circuit field effect transistors continues to increase, undesirable effects may originate at the corner of the device, i.e., in the channel region under the insulated gate near the isolation regions. It has been found that the electric field in the insulated gate near the isolation region may become enhanced, which may lead to a reduction of the threshold voltage of the channel in that region compared to the threshold voltage of the channel remote from the isolation region. The lower threshold voltage may provide a parallel path for current conduction, which has different turn-on characteristics, and may adversely affect the performance of the device. Corner effects and potential techniques to reduce corner effects are described, for example, in U.S. Pat. No. 5,998,848 to Brown et al., entitled Depleted Poly-Silicon Edged MOSFET Structure and Method, and U.S. Pat. No. 6,432,783 to Lee, entitled Method for Doping a Semiconductor Device Through a Mask. 
It is also known that the silicide contacts may produce unwanted effects adjacent the isolation region. Accordingly, techniques have been developed to pattern silicide contacts to avoid a boundary between a source/drain region and an isolation region remote from a channel region, as described, for example, in Korean Published Patent Applications 10-2004-0008631, 10-2004-0001907 and 10-2004-0001894.